文章摘要
王宇,刘崇茹,李庚银,等.适用于FPGA的模块化多电平换流器电容电压均衡控制方法[J].电力系统自动化,2019,43(8):167-173. DOI: 10.7500/AEPS20180204002.
WANG Yu,LIU Chongru,LI Gengyin, et al.Capacitor Voltage Balancing Control Method for Modular Multilevel Converter Applicable for FPGA[J].Automation of Electric Power Systems,2019,43(8):167-173. DOI: 10.7500/AEPS20180204002.
适用于FPGA的模块化多电平换流器电容电压均衡控制方法
Capacitor Voltage Balancing Control Method for Modular Multilevel Converter Applicable for FPGA
DOI:10.7500/AEPS20180204002
关键词: 模块化多电平换流器  电容电压平衡  现场可编程门阵列  实时仿真  硬件在环
KeyWords: modular multilevel converter(MMC)  capacitor voltage balancing  FPGA  real-time simulation  hardware-in-the-loop
上网日期:2018-11-01
基金项目:广东电网公司科技项目
作者单位E-mail
王宇 新能源电力系统国家重点实验室(华北电力大学), 北京市 102206  
刘崇茹 新能源电力系统国家重点实验室(华北电力大学), 北京市 102206 chongru.liu@ncepu.edu.cn 
李庚银 新能源电力系统国家重点实验室(华北电力大学), 北京市 102206  
孙吉波 广东电网有限责任公司电力调度控制中心, 广东省广州市 510600  
伍双喜 广东电网有限责任公司电力调度控制中心, 广东省广州市 510600  
摘要:
      子模块电容电压均衡是模块化多电平换流器稳定运行的重要前提。针对传统均压控制方法排序计算量大、器件开关频率高的问题,从实际工程角度出发,提出了一种适用于现场可编程门阵列的新型电容电压平衡控制方法。根据正常运行时电容电压波动范围划分若干子区间,并依据实时采集到的电容电压将子模块匹配到相应的子区间分组内。在此基础上,针对电容电压在额定值附近的子模块,分组时考虑上一时刻的开关状态,并遵循尽量维持原有开关状态不变的原则进一步降低了器件的开关频率。在ML605-FPGA板卡中开发实现所提方法,并与实时数字仿真器组成硬件在环实时仿真系统。仿真实验结果验证了该方法的可行性与有效性。
Abstract:
      Sub-module capacitor voltage balancing is an important prerequisite for the stable operation of modular multilevel converter(MMC). In order to solve the problems of heavy computation burden and high switching frequency of devices, a novel capacitor voltage balancing control method applicable for field programmable gate array(FPGA)is proposed from the perspective of practical engineering. Several sub-intervals are divided according to the fluctuation range of capacitor voltage during normal operation, and sub-modules are matched into the corresponding sub-intervals according to the capacitor voltage measured in real-time. On this basis, for the sub-modules with capacitor voltage near the rated value, the switching state at the last control period is considered when grouping, and the switching frequency is further reduced according to the principle of keeping the original switching state unchanged as much as possible. The proposed method is developed and implemented in ML605-FPGA board, and a hardware-in-the-loop real-time simulation system is built with the real-time digital simulator. The simulation results verify the feasibility and effectiveness of the method.
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